Large topology MEMS structures have applications for actuators, where the actuation force can be greatly increased by increasing the actuator area; optical devices, where high aspect ratios are needed to interact with optical beams, bio-MEMS, where high aspect ratio channels and sensors may be required; and a number of other applications where it is desirable to use a semiconductor compatible process to generate large topology structures.
A number of methods currently exist for forming large topology structures in MEMS processes, however, all have distinct disadvantages in process compatibility with following steps and/or in process complexity.
One common approach uses deep UV or X-ray lithography to define high aspect ratio features in photoresist or polymer and then electrodeposit metallic material inside the photoresist features. However, once the photoresist or polymer is removed, tall features are left on the wafer, preventing the use of standard resist and deposition processes for further processing. Also, the use of metallic materials to form the features prevents high temperature steps in further processing. Finally, this method requires the use of expensive X-ray lithography sources, which are not commonly used in semiconductor processing, for forming features.
Another method uses standard photoresist processing followed by a deep anisotropic etch (for example into the device layer of an SOI wafer) to form deep features. As in the previous method, this process leaves tall features on the wafer, preventing further standard processing. If the trenches formed by this process are narrow enough, they may be planarized by depositing a conformal film of sacrificial material, however, in this case the features are limited to having very small trenches (typically 2 μm or less in depth) significantly limiting the types of structures that may be defined.